2026-06-02 東北大学
図1. (a)半導体集積回路製造プロセスを用いてシリコン基板上に形成された検証チップの写真。(b) スピントロニクスPビットの断面構造の模式図。トランジスタと下層の配線を米国SkyWater Technology社で作製後、東北大学電気通信研究所附属ナノ・スピン実験施設にてスピン素子を形成。(c,d) 確率的に状態がゆらぐように設計されたスピン素子の断面,平面電子顕微鏡像。
＜関連情報＞
- https://www.tohoku.ac.jp/japanese/2026/06/press20260602-02-pbit.html
- https://ieeexplore.ieee.org/document/11535457
130nm CMOS集積超常磁性トンネル接合型pビット 130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit
Ju-Young Yoon; Nuno Caçoilo; Advait Madhavan; Jabez J. McClelland; Shun Kanai; Hideo Ohno,…
IEEE Electron Device Letters Published:26 May 2026
DOI:https://doi.org/10.1109/LED.2026.3696800
Abstract
Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.
