2026-08-18 清華大学
PMoE concept, on-chip architecture, and data-processing workflow
＜関連情報＞
- https://www.tsinghua.edu.cn/en/info/1245/15009.htm
- https://www.nature.com/articles/s41467-026-73983-4
スケーラブルなマルチタスクオンチップ光ニューラルネットワークのためのフォトニック混合エキスパート Photonic Mixture-of-Experts for scalable multi-task on-chip optical neural networks
Wencan Liu,Zhenghang Zhang,Peng Meng Chan,Run Sun,Yutong He,Yuhao Wang,Caihua Zhang,Sigang Yang,Tingzhao Fu,Yuyao Huang,Chaoran Huang & Hongwei Chen
Nature Communications Published:03 June 2026
DOI:https://doi.org/10.1038/s41467-026-73983-4
Abstract
Photonic computing offers an energy-efficient, high-bandwidth platform for artificial intelligence (AI) but currently faces scalability bottlenecks stemming from depth-dependent designs, linear optical structures, and intrinsic optical losses, along with high hardware and reconfiguration costs for multi-task processing. Here, we present a scaling paradigm that circumvents these limitations by expanding network width rather than depth, leveraging the intrinsic parallelism of photonics. We implement a scalable Photonic Mixture-of-Experts (PMoE) architecture, where parallel photonic cores function as expert networks. By dynamically routing inputs to these experts, the PMoE efficiently executes multi-task workloads without altering the physical optical weights. We fabricated a PMoE chip integrating three collaborative diffraction-based expert networks, featuring 18 parallel kernels within a compact intrinsic computational-core footprint of 0.067 mm2. Experimentally, the PMoE chip achieves multi-domain image classification with an average accuracy of 97.1%. While offering further scalability, this approach outperforms conventional optical networks and reduces digital parameter overhead by 67%. Our work underscores the scalability and efficiency of the PMoE architecture for next-generation large-scale photonic AI processors.
