2025-08-11 コロンビア大学
The latest chip, soon to be installed, precisely digitizes selected signals, capturing details that no existing component could reliably record. Credit: Ray Xu and Peter Kinget
＜関連情報＞
- https://www.engineering.columbia.edu/about/news/engineering-next-generation-experimental-physics
- https://ieeexplore.ieee.org/document/11017335
- https://iopscience.iop.org/article/10.1088/1748-0221/17/05/P05024
- https://www.sciencedirect.com/science/article/abs/pii/S0168900217300256
ATLAS液体アルゴンカロリメータの読み出し用放射線耐性8チャンネル15ビット40MSPS ADC A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout
Rui Xu; Jaroslav Bán; Sarthak Kalani; Chen-Kai Hsu; Subhajit Ray; Brian Kirby,…
IEEE Open Journal of the Solid-State Circuits Society Published:28 May 2025
DOI:https://doi.org/10.1109/OJSSCS.2025.3573904
Abstract
The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.
ATLAS液体アルゴンカロリメータのフェーズIトリガー読み出し電子回路のアップグレード The Phase-I trigger readout electronics upgrade of the ATLAS Liquid Argon calorimeters
G. Aad, A.V. Akimov, K. Al Khoury, M. Aleksa, T. Andeen, C. Anelli, N. Aranzabal, C. Armijo, A. Bagulia, J. Ban,…
Journal of Instrumentation Published: 16 May 2022
DOI: 10.1088/1748-0221/17/05/P05024
Abstract
The Phase-I trigger readout electronics upgrade of the ATLAS Liquid Argon calorimeters enhances the physics reach of the experiment during the upcoming operation at increasing Large Hadron Collider luminosities. The new system, installed during the second Large Hadron Collider Long Shutdown, increases the trigger readout granularity by up to a factor of ten as well as its precision and range. Consequently, the background rejection at trigger level is improved through enhanced filtering algorithms utilizing the additional information for topological discrimination of electromagnetic and hadronic shower shapes. This paper presents the final designs of the new electronic elements, their custom electronic devices, the procedures used to validate their proper functioning, and the performance achieved during the commissioning of this system.
CERN LHCにおけるATLAS液体アルゴンカロリメータ読み出し電子回路のアップグレード用、放射線耐性型デュアルチャンネル12ビット40MS/s ADCプロトタイプ A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC
J. Kuppambatti, J. Ban, T. Andeen, R. Brown, R. Carbone, P. Kinget, G. Brooijmans, W. Sippach
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment Available online: 16 January 2017
DOI:https://doi.org/10.1016/j.nima.2017.01.025
Abstract
The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented. The design consists of two pipeline A/D channels each with four Multiplying Digital-to-Analog Converters followed by 8-bit Successive-Approximation-Register analog-to-digital converters. The custom design, fabricated in a commercial 130 nm CMOS process, shows a performance of 67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5 ns (to first bit read out), while its total power consumption is 50 mW/channel. The chip uses two power supply voltages: 1.2 and 2.5 V. The sensitivity to single event effects during irradiation is measured and determined to meet the system requirements.
