2026-01-22 カリフォルニア大学アーバイン校（UCI）
A new silicon chip wireless transmitter developed by electrical engineers at UC Irvine enables data transmission speeds rivaling fiber optic cables at high energy efficiency. Labelled components on the chip include PRBS, pseudo-random bit sequence generator; LO, local oscillator; QPSK, quadrature phase-shift-keying; Sub-TX, sub-transmitter block; SPI, serial peripheral interface; and antenna. Payam Heydari / UC Irvine
＜関連情報＞
- https://news.uci.edu/2026/01/22/uc-irvine-engineers-invent-wireless-transceiver-rivaling-fiber-optic-speed/
- https://ieeexplore.ieee.org/document/11344822
- https://ieeexplore.ieee.org/document/10833751
アンテナからビットへのFバンド120Gbps CMOS RF-64QAM受信機 An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver
Youssef O. Hassan; Mohammad Oveisi; Zisong Wang; Payam Heydari
IEEE Journal of Solid-State Circuits Published:12 January 2026
DOI:https://doi.org/10.1109/JSSC.2025.3648748
Abstract
A CMOS 100–140-GHz end-to-end receiver (RX) is presented that integrates the antenna input all the way to the bitstream output, while demodulating 64QAM/16QAM/QPSK entirely in the analog domain. A sequential asynchronous demodulation method enables 120-Gbps operation at a notably small baseband power consumption. Fabricated in a 22-nm FDSOI CMOS process, the RX achieves a peak conversion gain of 32 dB and a minimum noise figure (NF) of 9.5 dB. A wireless link measurement over a 15-cm distance demonstrates real-time demodulation of QPSK, 16QAM, and 64QAM at error vector magnitudes (EVMs) of −12, −17.5, and −17.2 dB, respectively. The RX prototype occupies a die area of 2.5×3 mm2, including pad ring and test structures, and consumes 230 mW of power. This work underscores the feasibility of implementing low-power, sub-THz, high-speed RXs in nanoscale CMOS.
FutureGワイヤレスリンク向けビット・アンテナFバンド120Gb/s CMOS RF-64QAMトランスミッタ A Bits-to-Antenna F-Band 120-Gb/s CMOS RF-64QAM Transmitter for FutureG Wireless Links
Zisong Wang; Huan Wang; Youssef O. Hassan; Payam Heydari
IEEE Journal of Solid-State Circuits Published:08 January 2025
DOI:https://doi.org/10.1109/JSSC.2024.3523842
Abstract
This article presents a bits-to-antenna wireless transmitter (TX), fully integrated in 45-nm CMOS SOI, capable of surpassing 100-Gb/s data rates. The unique method of directly forming the 64QAM constellation within the RF domain, using three QPSK sub-TXs with controlled amplitude weighting, effectively mitigates the complications introduced by power amplifier (PA) nonlinearity in high-order modulations. This strategic approach opens avenues for significant enhancements in bandwidth and output power. This article further explores additional advantages of this TX design, such as local oscillator (LO) leakage suppression and improved output power, while going through the specifics of circuit block implementations. With a 40-GHz RF bandwidth, the RF-64QAM TX prototype achieves a measured data rate of 120 Gb/s with an effective isotropic radiated power (EIRP) of 16 dBm.
